DREAMPlaceFPGA
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This work aims to accelerate the different stages involved in FPGA placement - global placement, legalization and detailed placement, using the Pytorch deep-learning toolkit. Placement in the FPGA design flow determines the physical locations of all the heterogeneous instances in the design. ...learn more
Project status: Under Development
oneAPI, Artificial Intelligence
Groups
Student Developers for oneAPI
Intel Technologies
Intel CPU
Overview / Usage
Modern Field Programmable Gate Arrays (FPGAs) are large-scale heterogeneous programmable devices that enable high performance and energy efficiency. Placement is a crucial and computationally intensive step in the FPGA design flow that determines the physical locations of various heterogeneous instances in the design. Several works have employed GPUs and FPGAs to accelerate FPGA placement and have obtained significant runtime improvement. However, with these approaches, it is a non-trivial effort to develop optimized and algorithmic-specific kernels for GPU and FPGA to realize the best acceleration performance. In this work, we present DREAMPlaceFPGA, an open-source deep-learning toolkit-based accelerated placement framework for large-scale heterogeneous FPGAs. Notably, we develop new operators in our framework to handle heterogeneous resources and FPGA architecture-specific legality constraints. The proposed framework requires low development cost and provides an extensible framework to employ different placement optimizations.
As a first step, we have accelerated the global placement stage of FPGA placement. We are currently working to accelerate the other placement stages such as legalization and detailed placement.
Methodology / Approach
This work presents DREAMPlaceFPGA, an open-source, accelerated FPGA placement framework built on the PyTorch
deep-learning toolkit. We build an accelerated placement framework for heterogeneous FPGAs by integrating the ASIC DREAMPlace placer and the FPGA non-linear elfPlace placement algorithm. With a high-level programming interface in Python, the framework handles heterogeneity of FPGA resources and various architecture-specific legality constraints using newly developed optimized operators in C++/CUDA. DREAMPlaceFPGA outperforms both the CPU and GPU versions of elfPlace [7] in terms of global placement runtime, with similar placement quality.
Technologies Used
Intel CPU
Pytorch deep-learning toolkit
Nvidia GPU
Repository
https://github.com/rachelselinar/DREAMPlaceFPGA