Overview / Usage

The FPGA-Based Multi-ADC Interface project aims to develop a flexible solution for interfacing multiple Analog-to-Digital Converters (ADCs) in parallel using the Soft Bit Pattern Generator. The project will be implemented on an FPGA, with the original target platform being the Altera DE1-SoC board.

The main objective of this project is to leverage the capabilities of the FPGA to interface with more than one ADC concurrently through its GPIO (General Purpose Input/Output) pins. The Soft Bit Pattern Generator, already synthesized for the FPGA, will serve as the crucial component responsible for generating the necessary control signals and data patterns to communicate with the multiple ADCs.

The chosen ADC for this project is the AD7928, which is a high-performance, 12-bit, successive-approximation analog-to-digital converter. It offers a throughput of up to 1 Mega Samples Per Second (MSPS) when provided with a 20 MHz clock.

So far the signalCaptureBlock has been developed along with logic for DIN pins. DOUT capture requires the use of shift registers as highlighted in the system diagram. The top level module signalCaptureBlock can be implemented as of now.

Methodology / Approach

1. Data Sheet Study: The project started with an AD7938 ADC datasheet review to understand its specifications, functionalities, and timing requirements. Special attention was given to the timing diagram for the interface function to grasp the data communication process.
2. Critical Control Register Identification: The control register (12-bits wide Serial Input) was identified as the primary focus for writing data into the ADC. Its structure and configuration were analyzed to ensure correct communication with the ADC.
3. Digital System Architecture Development: A digital system architecture, called the "signalCaptureBlock," was designed to capture the ADC output efficiently. The architecture incorporated the necessary logic, including the DOUT logic, responsible for writing bits into the ADC's control register.
4. Verilog Implementation: The digital system architecture was translated into Verilog HDL (Hardware Description Language) using Intel Quartus Prime. The Verilog code represented the digital system's behavior and functionality.
5. Testbench Development: To validate the functionality and timing of the implemented architecture, testbenches were written (mimicking the behaviour of the ADC).
6. Simulation and Waveform Analysis: The Verilog design, along with the corresponding testbenches, was subjected to simulation using ModelSim. The simulation results were analyzed to verify the correct behavior of the signal capture block and to identify any potential issues or timing violations.
7. Iterative Design and Optimization: Based on the simulation results, iterative design and optimization were performed to rectify any identified issues and to fine-tune the digital system architecture for better performance.
8. Hardware Implementation: Once the Verilog design and simulations were satisfactorily validated, the design was synthesized and mapped to the target FPGA device using Intel Quartus Prime. The FPGA implementation aimed to achieve the desired functionality on the physical hardware.
9. Validation on FPGA: The FPGA-based system was tested on the Altera DE1-SoC board, where the Soft Bit Pattern Generator was initially developed. The performance of the ADC interfacing and signal capture block was validated using a 500 MHz oscilloscope with digital analysis capabilities.

FSM for user control will be developed on acquiring the necessary hardware.

Technologies Used

Intel Altera DE1-SoC Board (Cyclone V FPGA)

AD7928 ADC (Analog Devices)

Intel Quartus Prime

ModelSim

Verilog HDL and SystemVerilog

Repository

https://github.com/vishweswar/ADC.git

Other links

• AD7928 Datasheet
• Intel De1SoC manual