Overview / Usage

The Motorola SPI (Serial Peripheral Interface) protocol, commonly known as the four-wire SPI, is an established industry-standard serial interface for communication between microcontrollers and peripheral devices. In this project, I propose the development of a Soft SPI Controller synthesized on an FPGA, particularly targeting the Intel_DE1-SoC. While the DE1-SoC already features an SPI Master module, this soft controller offers a novel approach to enable multiple SPI devices to operate simultaneously and independently, thus providing greater parallel freedom.

The primary objective of this project is to design and implement a Soft SPI Controller on the FPGA that can interface with multiple SPI devices in parallel. By utilizing the FPGA's inherent flexibility, this solution enhances the traditional SPI interface, allowing multiple devices to be controlled individually, without contention, and operating concurrently at 1 Chip Enable (1CE) per device.

The traditional SPI interface supports multiple devices on the bus, but they typically share a single Chip Enable line, leading to sequential access and potential bottlenecks in multi-device communication. By developing a Soft SPI Controller on the FPGA, we seek to break free from this limitation and achieve true parallelism by independently controlling multiple SPI devices using individual Chip Enable signals.

Methodology / Approach

• Background Reading and Protocol Understanding: Background research on the SPI communication protocol was conducted, focusing on the different modes (CPHA and CPOL configurations) and their significance. Typical timing diagrams was studied to comprehend the data transfer sequence and synchronization requirements.
• Clock Configuration with On board PLL: The FPGA's onboard PLL (Phase-Locked Loop) was be configured to generate the required clock frequency for the SPI communication. The PLL settings was adjusted to meet the desired clock frequency, ensuring precise timing for SPI operations.
• Digital System Architecture Design: The digital system architecture was designed to implement the Soft SPI Controller. The architecture consists of separate modules to handle various aspects of the SPI communication, including clock operations (clockbox), shift register controllers, finite state machine (FSM), transmit (TX) and receive (RX) buffers, and logic for MOSI, MISO, SCLK, and CS_N lines.
• Verilog HDL Implementation: The Soft SPI Controller was coded in Verilog HDL using the Intel Quartus Prime. Each module can be implemented separately and then integrated into the main system architecture.
• Testbench Development and Simulation: Comprehensive testbenches developed to verify the functionality and timing of each module and the integrated Soft SPI Controller. Separate testbenches simulate the behavior of the Master and Receiver components. Simulation was performed using ModelSim to study and analyze the generated waveforms.
• Waveform Verification: The waveforms obtained from the ModelSim simulations was analyzed to validate the correct operation of the Soft SPI Controller. Timing constraints and signal integrity need to be assessed on an implementation basis.
• GPIO and Arduino UNO Integration: The data and clock lines from the FPGA will be routed to the GPIO pins to establish communication with an external Arduino UNO board (3.3V Logic). The physical connections will be made following the SPI protocol's standard pinout. The Arduino UNO will be configured as a Slave device.
• SPI Communication Setup: The FPGA will be set up to operate as the Master, and the Arduino UNO as the Slave. SPI communication will be established at an 8MHz clock frequency (adjustable) between the two devices.
• Functional Verification: The Soft SPI Controller's functionality will be rigorously verified through communication tests between the FPGA Master and Arduino UNO Slave. Data exchange and integrity will be validated at different clock frequencies to assess the system's robustness.

Technologies Used

Intel Altera DE1-SoC Board (Cyclone V FPGA)

AD7928 ADC (Analog Devices)

Intel Quartus Prime

Intel PLL IP

ModelSim

Verilog HDL and SystemVerilog

Repository

https://github.com/vishweswar/soft_SPI_master.git

Other links

• SPI Timing Diagrams
• DE1-SoC manual