Performance Evaluation of FPGA-based Hardware Accelerator for HPC applications
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In this project, we aim to find if FPGAs can be considered as a viable option as a hardware accelerator, and if so, how is their performance compared to existing processors like GPGPUs in various types of HPC workloads. We have an opportunity to take benefit of the recent developments in High-Level ...learn more
Project status: Under Development
oneAPI, HPC, Artificial Intelligence, Performance Tuning
Intel Technologies
DevCloud,
Intel Iris Xe,
Intel Iris Xe MAX,
Intel FPGA,
Intel® Xeon® Processors,
Intel CPU
Overview / Usage
High-performance computing (HPC) applications are becoming more and more complex day by day and they are increasing their computational demand on processors. Previously, CPU-only systems were used for HPC applications, but to meet the ever-increasing processing demand, systems augmented with hardware accelerators as co-processors have emerged over the decade as alternatives to CPU-only systems. This has opened up opportunities for accelerators like General Purpose Graphics Processing Units (GPUs), Intel Xeon Phi Many Integrated Cores (MICs), Field Programmable Gate Arrays (FPGAs), etc. to advance HPC to previously unattainable performance levels.
GPUs are now widely used as hardware accelerators for HPC systems, and, they are good at speeding up mostly data-parallel (SIMD) computations. Xeon Phi Many Integrated Cores (MICs) have been used in some HPC systems, but they have been discontinued by the manufacturer. However, recently, FPGA-based hardware accelerator cards and the associated tool-chain, i.e. Software Development Environment (SDE) are available from various vendors. We expect FPGA-based hardware accelerators may fare better for sequential and control-parallel applications.
FPGAs, though older than GPUs, were rarely deployed in the HPC applications. FPGAs were mainly used for embedded circuits and low-power digitals systems, hence, the suitability, and performance of FPGAs for HPC applications is largely unexplored.
Methodology / Approach
n the first phase, we have evaluated the performance of FPGAs compared to GPGPUs and CPUs, by using various synthetic micro benchmarks which are commonly used in scientific and engineering applications. For this purpose, we have ported the available C codes to OpenCL kernels. Then, those kernels were offloaded to FPGA and GPGPU. We have compared the performance with sequential execution on CPUs and kernel-based execution on GPUs. We have found that direct porting of CPU and GPU kernels to FPGAs mostly resulted in poor performance.
In the later phase, N-body simulation was developed in C for testing performance against sequential execution. The application was then ported to OpenCL so that computation can be distributed over several Work Items. Based on our experimentation we have observed that though FPGAs perform far better than sequential execution, but without intensive optimizations, FPGAs lag GPUs a lot.
We have also developed another application Particle Collision inside a box on C for similar evaluations and comparisons. We are planning to offload the second application for further experimentation and we will also try to bring out the impact of optimizations on performance in the later stage of our Project.
Technologies Used
We have assessed synthetic microbenchmarks and the application on following devices FPGA “Arria 10 GX”, GPU Iris Xe Max, CPUs Intel Xeon Gold 6128, Intel Core i9-10920X and Intel Xeon Silver 4114 .
We have used Intel Xeon Silver 4114 processor for assessing performance of sequential execution and C based codes were executed on this processor and execution time was noted.
For exploring better resources available on these devices OpenCL based codes were offloaded to FPGA “Arria 10 GX”, GPU Iris Xe Max, CPUs Intel Xeon Gold 6128, Intel Core i9-10920X . By using OpenCL code we could utilize multicores present on processors and GPU and pipelined parallelism on FPGA.